A semiconductor memory device is under developing, which includes three-dimensionally arranged memory cells. For example, a NAND type memory device includes a plurality of word lines stacked on a conductive layer and a semiconductor channel body extending through the word lines in the stacking direction, and memory cell transistors are disposed at portions respectively, where the semiconductor channel body intersects the word lines. Each memory cell transistor is operated by a voltage applied between each of the word lines and the semiconductor channel body which is electrically connected to the conductive layer. In such a device, there may be a case where ON-current for reading data out from a memory cell is lowered depending on a connecting structure between the conductive layer and the semiconductor channel body.